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Fabiano da Silva Catão
Departamento de Engenharia Elétrica, Universidade do Estado do Rio de Janeiro, RJ
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Dayane Mendonça Lessa
Programa de Pós-graduação em Engenharia Eletrônica, Universidade do Estado do Rio de Janeiro, RJ
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Cleiton Magalhães Freitas
Departamento de Engenharia Elétrica, Universidade do Estado do Rio de Janeiro, RJ
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Michel Pompeu Tcheou
Programa de Pós-graduação em Engenharia Eletrônica, Universidade do Estado do Rio de Janeiro, RJ
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Luís Fernando Corrêa Monteiro
Programa de Pós-graduação em Engenharia Eletrônica, Universidade do Estado do Rio de Janeiro, RJ
Keywords:
Phase-locked loop, Quadrature signal generator, Single-phase PLL, Second-order generalized integrator, All-pass filter, FPGA
Abstract
PLLs are synchronism circuits used in different applications ranging from signal processing to real-time algorithms applied to active power conditioners. The PLLs used in single- phase circuits can be composed by the association of quadrature signal generating circuits, such as the second-order generalized integrator (SOGI) or the all-pass filter (APF). The association of single-phase PLLs to quadrature signal generators results in a similar performance in comparison to three-phase PLLs, with no transient double-frequency oscillation. In this context, this work exploits the digital implementation in FPGA of SOGI-PLL and APF-PLL circuits through an approach based on high level synthesis (implemented in C++). A fixed-point architecture was applied to implement the PLL algorithms in 2MHz interrupts. In this case, the developed IPs (Intellectual Property) represented each of the PLLs through the included tools in the Xilinx Software VIVADO 2020.2. In this paper, there are simulation and experimental results through the FPGA. In both cases, the proposed digital implementation tracked the input signal over a period of approximately 0.06s.
